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【Final Information】 The circuit diagram could not be corrected to R23 = 181 → 221 on the main board. Final circuit diagram and handling Final circuit diagram (210103) operating instructions 【The case arrives and is assembled and completed.】 December 25, 2020    【Precautions for Use】 Basically, it has two built-in oscillators, and when used as a normal SG, one oscillator is often used. When using it as a single signal output, the other oscillator should be set to X = inactive. When using both simultaneously in O = active state, use them as two signal outputs from the (F1+F2) terminals. When both are set to O = active state simultaneously and used from the F1 or F2 output, there will be crosstalk, which although it depends on the terminal will be less than -70dB, but when used from F1 or F2, they should be used as a single signal output. The waveform below was observed at the F1 output terminal, outputting F1 = 30605MHz, F2 = 3.606MHz, comparing both = O state with only F2 = X state.  【Summary of items that have been revised since the start of the program up until November 14th】 ① Cut the pattern of U7 (⑪) (bare board state) and wire ⑪ to GND after mounting. See ⑧ in [Adjustment and Operation Check] below. Cause = U7 (counter) cannot start. ② Display board R2 = R3 = 103 → 393 Cause = Large chattering variation in Akizuki's rotary encoder. ③ Main board R10 = R32 = 272 → 222, R2 = R12 = R31 = R44 = 561 → 681 Reason = Level setting change. ④ CPU unit chip capacitors C1 = C5 = 104 → 105, tantalum C2 = C4 = C6 = 22/16 → 47/16 I would like to summarize the factors as supplied parts. ⑤ Since the only chip type available for L3 = L6 = L11 = L14 = 0.39uH on the main board was the chip type, some ingenuity was required for installation.  ① Modify the main circuit diagram Main circuit diagram 1114 The rest is reflected in the previous circuit diagram 1108. 【operation manual】 Most of the basic operations have been covered in the explanation so far, so I don't think it's necessary, but I'll explain a few points anywa In the unlikely event that the device becomes unreliable and does not operate normally during operation, or if turning the power off and on still results in an abnormality, press the "←" key + "→" key to turn the power switch on. This will initialize the device. ① Memory function In normal mode, pressing the "MEM" key enters a mode for reading or writing memory.  The memory has a total of 18 channels, which could be represented as M1 to M18, but for convenience when adjusting the phase of the AFPSN, there are 9 channels in the M-L column and 9 channels in the M-U column, for a total of 18 channels. To read or write to the L column box or U column box, select the L column box with the Left key or the U column box with the Right key. As an example, let's try the L column box by pressing the Left key.  If you press the "→"Right key, it will create a U-column box.  This is an M-L column box. You can write/read the frequencies of channels 1 to 9 in this box. Try pressing "1".  This determines whether you want to read or write the frequency of the M-L1. To read, press the "0" (Read) key.  The word “Read” will appear, the memorized frequency will be output, and the device will enter normal mode.  In this case, the pole frequency of the first row of L = 5.6782Hz is output. The frequency to be memorized can be either F1 or F2. Next, try writing to memory. The procedure is the same as above up to the point where the channel is specified. At this point, you can decide whether to read or write. If you are writing, press the "." Write key, but before that, in normal mode, set the frequency you want to write to, either F1 frequency or F2 frequency.  When writing, the word "Write" appears and the mode switches to normal. In other words, when outputting the pole frequency of AFPSN, for example, when generally adjusting in 8 steps, the frequencies of the 1st to 8th steps of L column and the 1st to 8th steps of U column are set for each step. Also, even if it is unavoidable to change the connection of the measurement points, which was done with one oscillator, inputting the frequency value each time can cause mistakes. By using this memory function, for example, the frequencies of the 1st to 8th steps of L column can be written in F1 in the boxes of M-L column 1 to 8, and the frequencies of the 1st to 8th steps of U column can be written in F2 in the boxes of M-U column 1 to 8. This way, there is no need to bridge the two inputs (L column and U column) when adjusting, and you can connect the F1 output to the L column input and the F2 output to the U column input, and then adjust by just reading the memory. ② Output Level Adjustment Pressing the "FA" key will move the cursor to the output level value. In this state, turning the rotary encoder will allow you to vary the output level from -30 dBm to +8 dBm in 1 dB steps. ③How to use the "←" Left key and "→" Right key Use the right key to move the cursor to the desired digit and use the encoder to increase or decrease the frequency. ④ If you accidentally press an unwanted number while entering a frequency using the numeric keypad, press the "SP" (Cancel) key to return to the original value. 【Adding measurement results】 ① Frequency deviation when a nuclear power plant (20.48 MHz) is locked in to an external 10 KHz and when it is unlocked.  ② Phase deviation of I/Q signals I checked from 10Hz to 3KH, but I tried checking in the 10Hz to 30KHz band (30KHz) used by AFPSN. When I checked and measured the sweep settings, Start = 10Hz, Stop = 30KHz, Time = 20 seconds, the phase error was 0.01 degrees, which probably suggests that there is an error in the phase meter.  【Measurement results】 ① (F1+F2) output terminal signal ・Two audio signals (1KHz + 1.5KHz)   ・RF signal (3.6000MHz+3.6005MHz) RF2 signal   ・RF signal (7.1500MHz+7.1505MHz) RF2 signal  ② Checking the Sweep Operation It starts with the "SP" key. Each time you press the "SP" key, it switches between "Start frequency" → "Stop frequency" → "Sweep time" → "Normal mode". The sweep operation starts when you press the "→" right arrow key anywhere outside of "Normal mode". Pressing the "→" key again during the operation stops the sweep. The "→" key will repeat start/stop. To escape from the sweep state and switch to normal mode, press the "SP" key while stopped to switch to "Normal mode". For example, Start frequency setting---set to 10Hz  Stop frequency setting --- set to 3KHz  Sweep time setting --- Set to 10 seconds. Press the "Hz" key for seconds.  Pressing the left arrow key starts a sweep motion.  Start frequency = 10Hz Stop frequency = 3KHz Sweep time = Left = 10 seconds, Right = 20 seconds Video on the right with the phase meter directly below, the meter on the right is irrelevant. Red needle = input level, ideally 3Vpp input for homemade phase meter, so output set = 07dBm, input F1 I output and Q output to phase meter to check phase difference. In the video on the right, the phase needle swings due to noise in the return on the 10Hz side, but there is no noise on the 3KHz side, so I checked the phase error between 3KHz and 10Hz, but there was almost no error The range of the phase meter is ±0.1 degrees.   【Adjustment and operation check】 ① Display unit current consumption check, +5V single power supply with CPU unit attached --- approx. 20mA ② LCD common adjustment---Adjust VR1 so that the white characters are most visible. ③ LCD display when +5V is applied.  ④ Check the response of each key press. ⑤ Check the current consumption of the main unit If you do not install the ±5V 3 terminals and PQ3R, but connect +3.3V/±5V to a bench power supply and supply power, the LCD display will be as shown above, with 3.3V = 0.42A, +5V = 0.08A, -5V = approximately 0.06A. ⑥ Main board offset adjustment In the above display state, if you press and hold the "FS" key for 0.5 seconds or more, F1 will change from active to inactive, and F1 will become X, F2 will become X, and both signals will become inactive.  In this state, 3.3V = 0.15A, ±5V = the same. The maximum 3.3V current can be close to 0.9A. Offset adjustment at each output terminal ⑦ Check the operation of each output terminal Makes both F1 and F2 active. Each time you press the "FS" key, it switches between F1 and F2. Also, if you press it for more than 0.5 seconds, it will alternate between ON and OFF.  The specified frequency is output at 3.1 Vpp at each output terminal, and there is a 90 degree phase shift between the I/Q signals.  (F1+F2) Output terminal: 2 signals of 1KHz + 1.5KHz  ⑧ Checking external reference clock (10KHz) lock operation ＜There are some areas that need to be fixed.＞ ・No. ⑪ (CLEAR terminal) of U7 (74HC4040) is wired to the +B line. This terminal needs to be L (GND), so cut the pattern and wire No. ⑪ to GND after installing the IC. ・When inserting R25 (digital transistor output resistor), insert it in the opposite direction to the silk screen printing. This has no effect on operation, but is used as a confirmation point.  Video of locking in to an external reference clock. Input is turned OFF/ON. Locks instantly when input is turned ON.   【Production】 Production Instructions 【design】 Circuit Diagram 1108 Parts list 1108 From past experience, it is desirable to eliminate connectors (connector wires) as much as possible. The power supply unit will not be independent, but will be integrated into the main board, and will only supply 100V AC. We considered using an FFC cable instead of a connector wire to connect the display unit and main unit, but it was too expensive (it could not be made into a standard product due to its length). Therefore, we decided to use a connector wire this time as well. mainBlock ① The functional requirements for the DDS to be used were: ・Able to drive a clock of 30MHz x 6 times or more. ・Able to output I and Q signals independently. ・Frequency register = 48 bits. ・Not finer pitch than SSOP. For these reasons, the AD9854 was selected. ② The system clock is driven at 20.48MHz x 9 = 184.32MHz. The reason for setting the clock at 20.48MHz is that 20.48MHz is locked to an external reference clock of 10KHz as a VCXO, and at this time, the frequency closest to 30MHz, which is 2 times the power of 2 of 10KHz, is 20.48MHz. 20.48MHz / 2^11 = 10KHz, and a single counter outputs a duty of exactly 50%. ③ The lock circuit of the nuclear power plant divides the 20.48MHz VCXO output by 1/2048 with 74HC4040 to create 10KHz, and the external reference clock 10KHz The two 10KHz signals driven by Q1 are phase-compared by X-OR of U5 (7SH86) and output at pin ④ at twice the frequency (20KHz). This is filtered by CR and supplied to the control terminal of the VCXO. When the external reference clock 10KHz is removed, the 10KHz (duty 50%) divided by U7 is output as is to the output of pin ④ of U5, and a voltage of Vcc/2 is supplied as the control voltage for the VCXO, so the deviation in the 20.48MHz unlock frequency is very small, and depending on the application, it is possible to use only the internal clock. The power supply voltage of this circuit is all 3.3V. ④ The power supply voltages are AD9854 = 3.3V, VCXO = 3.3V, CPU/counter etc. = 2.7-5V, so a single 3.3V supply would have been possible, but ±5V would have been required to obtain +10dBm for the output amplifier. Also, the LCD I purchased was a 5V product, not a 3.3V product, so the power supply circuit uses AC6V-2 windings for the secondary winding of the transformer, with one winding = +3.3V and the other winding = ±5V. By the way, the current consumption is 3.3V = maximum 1A, +5V = 80mA, -5V = 60mA. ⑤ Both I and Q DDS output signals are amplified to +8dBm at 50Ω output through a 35MHz 7th order LPF by a current feedback wideband op-amp. Since the output signal is output from 0.000001Hz (1uHz), C coupling is not possible. Since the DDS is a +3.3V single power supply, the output signal has a positive offset voltage, so the bias is adjusted to ±0V in each op-amp circuit using a 472 (502) semi-fixed VR. ⑥ The F1+F2 signal can output any two signals. For example, if the output level is set to F1 = +8 dBm and F2 = +8 dBm, the F1+F2 output terminal will have a Vpp = 3.1 Vpp, but in dBm each F1/F2 = 8 dBm - 5 dBm = +3 dBm. ⑦ The ladder resistor used in the control line is used to convert 5V to 3.3V, since CPU = +5V and DDS = +3.3V. DisplayBlock ① I've used this type of LCD many times in the past, and the COM (③) terminal is used to adjust the common bias of the LCD. I've heard in the past that some LCDs were defective and the characters were hard to read, but I set it to the most visible state with VR1. ② The key matrix is not static but operates dynamically, so no tricks can be made. ③ This rotary encoder uses a cheap mechanical type from Akizuki. Therefore, a chattering absorption circuit is also included in the hardware. There are two types of Akizuki (one with a wide leg pitch and one with a narrow leg pitch) and the terminals are not common, so JP1 to JP4 are compatible with both. 【SSG Specifications】 ① It outputs two independent signal sources (F1 and F2), and when both are active, it can output two signals. ② The output terminals are F1/F2/F1+F2, and F1 and F2 also output I and Q signals. ③ Output frequency is 0.000001Hz (1uHz) to 32MHz. External reference clock input = 10KHz. ④ The output level is -30dBm to +8dBm. No special attenuator is used, but it is controlled by the DDS function. The reason for the -30dBm is that the receiver's ANT terminal is -23dBm = S9 + 50dB, so this setting is OK, but to attenuate further, an external ATT is required. The reason for the +8dBm is that the phase adjuster of our homemade AF-PSN was measured with an input level of 3Vpp (+7dBm), and the maximum output was +8dBm. Frequency accuracy of 3 decimal places is also required. ⑤ Sweep Function You can set the start frequency, stop frequency, and sweep time and repeat the pattern forever. ⑥ Memory function A total of 18 channels can be secured, but this requires inputting each pole frequency when adjusting the AF-PSN (pole frequency of each stage). Furthermore, when inputting three decimal places, input errors can occur, so to prevent this, the frequency is stored in memory for each pole in the U and L columns and can be read out.  【Device Selection】 ① The oscillation source is a DDS, but the requirements for the DDS are the number of DAC bits, the number of frequency register bits, and the ability to output I and Q signals simultaneously. However, if the DAC is 14 bits and the frequency is 48 bits, the options are quite limited, and the shape is a BGA type, making simultaneous I and Q output difficult. Therefore, we decided to select a DDS (AD9854) that can output DAC = 12 bits, frequency = 48 bits, and I and Q. This consumes a lot of power and has a large number of pins (QFP80), but we have used it in our own builds in the past, so we decided to select it. However, these are quite expensive to procure domestically, so we will try to procure them from China. ② The high-frequency op-amp used to process the output signal is the AD8009 (current feedback type), and the power supply voltage is ±5V, so the output level islimited. ③ It uses a character LCD for the display, which costs ¥800 at Akizuki and other stores, but is ¥185 for a similar size model on Amazon, so I made an immediate decision. When I actually used it, the blue background of the Akizuki product was magenta, while the Marutsu Parts product was clean and not magenta, but expensive, while the Amazon product of course was clean and not magenta, and cheap. 【The story behind the production】 ① The HP standard signal generator (3325) broke. An error message appeared and I tried to repair it but was unable to do so. Even if I could restore it, it would be particularly deep and heavy, making it less practical. ② The "3DDS" I made previously was made to be a versatile carrier for various radio manufacturers, and of course it can also be used as an SSG, but the CPU used is old and cannot be upgraded. ③ I wanted a signal generator for measuring instruments that could oscillate continuously from audio (ultra-low frequency) to high frequency (HF), and the oscillation frequency had to be accurate to microhertz so that it could be used as a reference clock. I wanted a small and lightweight SSG. |
