| This IC is made
by using Maxim's MAX294 in a two-stage cascade. If you want to set the
cutoff frequency to 100 times the clock frequency, that is, 3.0KHz, you
can drive the clock at 100 times the frequency, 300KHz. You can freely set
the cutoff frequency by varying the clock frequency. MAX294 can be driven
by ±5V, but other 7000 series ICs are driven by a single 5V power supply,
so considering the D-range/SN, it is better to refrain from using it. In
my homemade machine, I use a single stage configuration rather than a
two-stage cascade. The problem is the clock generation method. There are
two methods: dividing the reference clock and varying the division ratio,
and configuring a PLL with a resolution of 10KHz and varying the cutoff
frequency in 100Hz steps. Each production machine uses the former method.
I also created the latter method separately, so I will introduce it here. |
Schematic File |
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| Measured
characteristics at Fc=3.0KHz |
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Creation from the primary clock division
The system clock for both the transmitter and receiver is 27MHz, and the
division ratio is changed based on this to generate the clock. This method
can cause the division ratio to be indivisible. For example, if the cutoff
is 3.0KHz, the clock needs to be 300KHz. 27MHz/90=300KHz is perfect. If
the cutoff is 3.1KHz, the clock needs to be 310KHz. 27MHz/87=310.34KHz,
and the actual cutoff is 3.1034KHz. The cutoff frequency has a resolution
of 100Hz and takes the least common multiple, so there is no problem. For
CPU control, set the division data to D0 to D7 and load it with LOAD. It
can also be set by SW instead of CPU. |
Schematic File |
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Creating with PLL
The advantage of this method is that by using a two-digit decimal SW, it
is easy to set, the display can be checked, and the clock frequency can be
generated exactly. If you want to set the cutoff frequency at 100Hz
resolution, a reference clock of 100Hz x 100 times = 10KHz is required for
the PLL circuit. Since the original oscillation clock (27MHz) of each
homemade device is locked from the external reference clock 10KHz created
from GPS, you can use this 10KHz reference clock as it is, or divide the
system original clock (27MHz) by 1/2700 to extract 10KHz and use it,
depending on the required PLL step resolution. For CPU control, you can
set A0 to D0 (the ones digit of the division ratio) and A1 to D1 (the tens
digit of the division ratio). For the decimal switch, the decimal switches
0 to 9 are used in two places, the ones digit and the tens digit. The SW
display is the cutoff frequency. For example, if the cutoff frequency is
3.0KHz, the tens digit SW = 3 and the ones digit SW = 0. If the cutoff is
3.0KHz, the required clock = 300KHz, and the set division ratio =
300KHz/10KHz = 30. If it is 3.1KHz, the required clock is 310KHz, and the
set division ratio = 310KHz/10KHz = 31. |
Schematic File |
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| PLL type SCF
control board |
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